FPGA Gurus | The latest news, blogs, applications and resources on FPGAs

Recent Blogs

Analog matters – more than you think

By Loring Wirbel May 14, 2012

Analog Devices seminars on using ADI converters with Xilinx FPGAs represent a trend the FPGA (and semiconductor) industry sorely needs.

Lattice announced production of SiliconBlue “Los Angeles”

By Loring Wirbel May 8, 2012

Lattice gains the first benefits of acquiring SiliconBlue, by moving the “Los Angeles” mobileFPGA into production.

Protocols to Go

By Loring Wirbel May 3, 2012

PLDA offers a new kind of IP core for Xilinx and Altera FPGAs, embedding TCP/IP protocols over AXI4 interconnect.

Achronix Aims 22-nm Process at Vertical FPGA Applications

By Loring Wirbel April 24, 2012

Achronix differentiates its new FPGAs from an Intel 22-nm process by designing for specific vertical markets – beginning with communication protocols.

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News Spotlight

Tabula’s ABAX 3PLDs are in the news

May 9, 2012

You may recall that the folks at Tabula have developed an innovative FPGA architecture that they refer to as ABAX 3PLDs. The idea is that they use a small piece of silicon that they reconfigure eight times for each user clock beat.

Use a twist (and other popular wires) to reduce EMI/RFI

May 9, 2012

Alexander Graham Bell patented twisted-pair wires in 1881. Remarkably, we still use them because they work so well.

eCROS platform now supports Xilinx Zynq-7000 EPP

May 8, 2012

eSOL's eCROS real-time OS-based integrated software platform now supports the Xilinx Zynq-7000 Extensible Processing Platform (EPP).

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Featured Resources

Meeting the Low Power Imperative at 28 nm

Whether you want to reduce your carbon footprint, reduce operating costs, or just be more energy efficient, Altera’s 28-nm devices enable system designers to increase their control over power consumption in today’s increasingly power-sensitive applications.

PRODUCT BRIEF: MachXO2 Consumer Applications

The MachXO2™ family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for low-power consumer applications such as smart phones, GPS devices and PDAs. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, MachXO2 devices provide a flexible “do-it-all” solution for consumer designs.

DATA SHEET: MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.

Tips and Techniques for 28-nm Design Optimization

Timing closure is of critical importance in high-speed FPGA designs. This white paper focuses on the challenges that affect timing closure and discusses how simple HDL changes can help resolve timing issues and reduce the time needed to achieve timing closure.

Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions

Because a fast and robust memory interface is crucial for many designers, Altera provides the fastest, most efficient, and lowest latency memory controllers, which allow designers to work with today’s higher speed memories quickly and easily. Designing with Arria V^® FPGAs not only helps to make designs successful but also ensures that implementation is fast and easy.

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Featured Video

Reduce Power by Removing External Compensation Components with Stratix V FPGAs

Watch this short demonstration of how our 28-nm Stratix V FPGA can provide you with the lowest jitter and bit error rate. In addition, you will see how system cost and power are reduced by removing external compensation components.

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