Blog Posts

Lattice expands ECP3 family in three directions

By Loring Wirbel January 24, 2012

Lattice expands its ECP3 family with tiny packages, faster speed, and lower power.

Kane Modules Meld Spartan-6 with TI, ADI Varieties of DSP

By Loring Wirbel January 20, 2012

Kane Computing tightens FPGA links with DSP by linking D.module and VITA 57 FMC form factors.

Pentek Debuts Onyx SDR Module Family Based on Virtex-7

By Loring Wirbel January 18, 2012

Pentek launches the first of its Onyx family of software-defined radio modules, using the Xilinx Virtex-7 for signal processing.

Xilinx Wins China Coverage on Growing Opportunities

By Loring Wirbel January 13, 2012

Peoples Daily Online gives primary coverage to the FPGA market, interviewing Xilinx APAC Director Vincent Tong.

Genetic Sequencing Meets Massively-Parallel Hardware

By Loring Wirbel January 11, 2012

CLC bio and SciEngines use massive banks of Spartan-6 FPGAs for nucleotide sequencing.

Lattice Shows off Stereo Camera at Consumer Electronics Show, with Sensor Help from Aptina

By Loring Wirbel January 6, 2012

Lattice demo at Consumer Electronics Show will show stereo camera based on MachXO2, with sensors from Aptina.

Xilinx to Spotlight Automotive Ethernet, Advanced 3D Displays at Consumer Electronics Show

By Loring Wirbel January 5, 2012

Xilinx will come to the Consumer Electronics Show with new solutions for automotive Ethernet, and for advanced TV displays.

The Year to Come in FPGAs

By Loring Wirbel January 2, 2012

FPGAs are poised to become the most common high-integration semiconductor device in all markets.

Rules for Randomization

By Loring Wirbel December 28, 2011

IP Cores Inc. replaces PRNG in many FPGAs with real random numbers.

Microsemi gets some crypto assistance from Invia, CRI

By Loring Wirbel December 19, 2011

Microsemi gains some security expertise for SmartFusion, other FPGAs, courtesy of INVIA SAS and CRI.

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Meeting the Low Power Imperative at 28 nm

Whether you want to reduce your carbon footprint, reduce operating costs, or just be more energy efficient, Altera’s 28-nm devices enable system designers to increase their control over power consumption in today’s increasingly power-sensitive applications.

PRODUCT BRIEF: MachXO2 Consumer Applications

The MachXO2™ family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for low-power consumer applications such as smart phones, GPS devices and PDAs. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, MachXO2 devices provide a flexible “do-it-all” solution for consumer designs.

DATA SHEET: MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.

Tips and Techniques for 28-nm Design Optimization

Timing closure is of critical importance in high-speed FPGA designs. This white paper focuses on the challenges that affect timing closure and discusses how simple HDL changes can help resolve timing issues and reduce the time needed to achieve timing closure.

Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions

Because a fast and robust memory interface is crucial for many designers, Altera provides the fastest, most efficient, and lowest latency memory controllers, which allow designers to work with today’s higher speed memories quickly and easily. Designing with Arria V^® FPGAs not only helps to make designs successful but also ensures that implementation is fast and easy.

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Optimizing 10-Gbps Backplane Performance on Stratix V FPGAs

With Altera’s Transceiver Signal Integrity Development Kit, Stratix® V GX Edition and the Transceiver Toolkit tool in Quartus® II software, you can easily and efficiently evaluate the performance of your high-speed serial transceivers.

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