Blog Posts

Analog matters – more than you think

By Loring Wirbel May 14, 2012

Analog Devices seminars on using ADI converters with Xilinx FPGAs represent a trend the FPGA (and semiconductor) industry sorely needs.

Lattice announced production of SiliconBlue “Los Angeles”

By Loring Wirbel May 8, 2012

Lattice gains the first benefits of acquiring SiliconBlue, by moving the “Los Angeles” mobileFPGA into production.

Protocols to Go

By Loring Wirbel May 3, 2012

PLDA offers a new kind of IP core for Xilinx and Altera FPGAs, embedding TCP/IP protocols over AXI4 interconnect.

Achronix Aims 22-nm Process at Vertical FPGA Applications

By Loring Wirbel April 24, 2012

Achronix differentiates its new FPGAs from an Intel 22-nm process by designing for specific vertical markets – beginning with communication protocols.

Xilinx Launches Vivado Design Environment for All New Virtex-7 Users

By Loring Wirbel April 24, 2012

Xilinx re-architects all design tools into Vivado EDA suite as FPGAs move to 28-nm family.

Microsemi Claims 10,000 Space-Hardened FPGAs

By Loring Wirbel April 23, 2012

Microsemi claims milestone of 10,000 rad-hard FPGAs shipped for space applications, though parent company has had parts in space vehicles since 1957.

Altera and Eutecus; Lattice and Huawei

By Loring Wirbel April 20, 2012

More team playing was announced in mid-April, with Altera and Eutecus expanding video analytics, while Huawei praised Lattice as a “core partner.”

Xilinx Hits NAB with 4K Developments, New BBC Design

By Loring Wirbel April 16, 2012

Xilinx is continuing its high-resolution drive at the National Association of Broadcasters, with a unique design with the BBC, and further developments in 4k displays.

Brocade Weighs in on the FPGA/ASIC Debate

By Loring Wirbel April 12, 2012

Brocade blog discusses the place for FPGAs and ASICs in routers and switches for the service provider community.

Stratix V Again – But in Networking?!

By Loring Wirbel April 9, 2012

Altera’s latest design win for Stratix V is in a field where new designs are few and far between – high-speed networking.

Featured Resources

Meeting the Low Power Imperative at 28 nm

Whether you want to reduce your carbon footprint, reduce operating costs, or just be more energy efficient, Altera’s 28-nm devices enable system designers to increase their control over power consumption in today’s increasingly power-sensitive applications.

PRODUCT BRIEF: MachXO2 Consumer Applications

The MachXO2™ family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for low-power consumer applications such as smart phones, GPS devices and PDAs. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, MachXO2 devices provide a flexible “do-it-all” solution for consumer designs.

DATA SHEET: MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.

Tips and Techniques for 28-nm Design Optimization

Timing closure is of critical importance in high-speed FPGA designs. This white paper focuses on the challenges that affect timing closure and discusses how simple HDL changes can help resolve timing issues and reduce the time needed to achieve timing closure.

Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions

Because a fast and robust memory interface is crucial for many designers, Altera provides the fastest, most efficient, and lowest latency memory controllers, which allow designers to work with today’s higher speed memories quickly and easily. Designing with Arria V^® FPGAs not only helps to make designs successful but also ensures that implementation is fast and easy.

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Featured Video

Reduce Power by Removing External Compensation Components with Stratix V FPGAs

Watch this short demonstration of how our 28-nm Stratix V FPGA can provide you with the lowest jitter and bit error rate. In addition, you will see how system cost and power are reduced by removing external compensation components.

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