Lattice Semiconductor Corp. has gained some advantages by exploring the mid-range of FPGA performance.  The company has taken the core of its popular ECP3 FPGA to create the new ECP4, which offers 6-Gbit serializer-deserializer (Serdes) interfaces with low enough power consumption to place the FPGA in a traditional wire-bond package.

Doug Hunter, vice president of corporate marketing at Lattice, said the intent has been conscious for a few years running to avoid chasing Xilinx and Altera in absolute density, but instead opt for low power and small footprint in mid-range densities.  The focus served the company well with ECP3, and Lattice is expecting a repeat performance for ECP4.

Lattice has developed hard IP for its four-input lookup table (LUT) architecture, which currently scales to 250,000 LUTs, with a target of up to 500,000 LUTs for the ECP4.  Shakeel Peera, director of silicon marketing at Lattice, said that several advantages fall out of such a mature 65-nm process, including the low-power Serdes.  A “soft” clock and data recovery (CDR) has been designed for use with LVDS interfaces, for example, and Power sysDSP cores allow the company to design a range of DSP filters in a more cost-effective manner than those used in larger FPGAs.  ECP4 supports high-speed memory interfaces, including DDR3, using pre-engineered source synchronous support on chip.

Lattice is taking maximum advantage in ECP4 of an earlier concept at hard block definition it calls “Masked Array for Cost Optimization”, or MACO (http://www.latticesemi.com/products/fpga/ecp4/macocommunicationengines.cfm?source=sidebar).   At the end of each embedded RAM block row, Lattice offers a structured ASIC block called MACO, which in ECP4 is used for communication duties.  The blocks can be used for tri-speed or 10G Ethernet MACs, for Serial RapidIO interfaces, or for PCI Express 2.1.  Using the MACO blocks can profoundly lower power dissipation, and eliminate the use of as many as 100,000 LUTs compared to a ground-up communication interface design.  Combining the low-power Serdes, MACO blocks, and soft CDR provides unprecedented density for applications such as Ethernet line cards.

The ECP4 family will debut with six family members, ranging in size from the ECP4-30 with 33,000 LUTs, a single MACO engine, four Serdes channels, and 18 CDRs; to the ECP4-250, with 244,000 LUTs, quad MACO engines, 16 Serdes channels, and 40 CDRs.  The Diamond 1.4 design suite that supports ECP4 is out in beta release now.  The first ECP4 devices will be sampling in the first half of 2012, with production slated for the second half of the year.