A question that has been nagging me since Tabula introduced its new time-slotted virtual 3D FPGA architecture last March was, how can one design logic structures with such a radical new topology.  Tabula now has addressed the question with its http://www.tabula.com/news/news_Stylus-02-15-2011.phphttp://www.tabula.com/news/news_Stylus-02-15-2011.php, and the answer is – exactly the same as one would design with traditional FPGAs.

Given the significant and radical steps Tabula is taking in multiplexed on-chip channels, development of a software suite capable of handling legacy design concepts was no mean parlor trick.  But Rajeev Jayaraman, vice president of software development at Tabula, called it a critical goal in Stylus development – making sure the use of what Tabula calls the “spacetime” architecture of its ABAX devices was transparent for customers familiar with traditional design methodology.

Both behavioral synthesis and component place and route had to be provided in a manner that hid details of Tabula’s “time vias,” transparent latches that reconfigure the design in a time domain, from the designer.  The customer uses a browser-based design tool that takes traditional RTL design and maps it into the Spacetime architecture, using VHDL, Verilog, or System Verilog as inputs.  Stylus then uses a timing-driven place and route to optimally place components of the design across the virtual 3D architecture.  During the design process, the customer can switch between logical, physical, and schematic product views.

Given IT trends in software use, it’s no surprise Tabula elected to design Stylus to be cloud-based from the outset, thus moving beyond traditional seat- and site-license concepts of using EDA tools in the FPGA industry.  Customers can configure Tabula’s own Mega Lookup Table and RAM block components, as well as third-party IP blocks for DDR2 and DDR3 memory controllers, PCI Express Gen 2 interfaces, 1G and 10G Ethernet MACs, Serial RapidIO, and the ColdFire CPU from Freescale.

And speaking of serial interfaces, Tabula is releasing an evaluation kit simultaneously with the Stylus software, in which an ABAX A1EC04 FPGA is integrated on a PCI Express board along with 72 Mbytes of QDR II RAM, and a full gigabyte of DDR3 RAM, using an LP-DIMM socket.  The $7500 development kit includes five separate 10M/100M/1G Ethernet interfaces, as well as x1 and x8 PCI Express connectors.  And of course, the development kit gives you access to the cloud-based Stylus suite.