A Vancouver-based EDA startup has a new concept for “dialing up” optimized levels of hardware visibility for real-time debugging and validation of FPGAs – as well as ASICs and Systems on a Chip (SoCs).  Veridae Systems Inc. is launching its Clarus Silicon Validation Suite this month, offering a means of inserting hardware trigger points in designs, requiring only 1 to 3 percent of FPGA area for optimal visibility.

Brad Quinton, chief technology officer of Veridae, said many core concepts were developed by the Veridae team at University of British Columbia, when the designers looked at the limitations of design validation in software debug, hardware emulation, and hardware acceleration methods.  Traditionally, ASICs were emulated in hardware systems that once were the size of mainframe computers, but eventually shrunk to add-in cards.  Verifying an FPGA design in another FPGA implemented in an emulator or accelerator is interesting, Quinton said, but cannot provide the visibility of thousands of internal state machines and signals within a new design.

The Clarus suite begins with a tool called Implementor, that examines an RTL-level design and looks for optimal points to insert hardware triggers.  Implementor will automatically discover clocks, generate test scripts, and prioritize points through an OptiRank algorithm.  It generates an optimal signal capture infrastructure, and can create the logic blocks for that infrastructure.

The Clarus Infrastructure includes a hardware-based Access Control point and Router.  This tool can interface with existing JTAG controllers and with CPUs that use advanced interconnects such as AMBA.  The Router collects information from hardware-based “Capture Stations”, which may be implemented as a single station within a complex FPGA, or multiple stations across many FPGAs.  Stations can be cascaded so that a trigger from one could set off a trigger point in a second station.

The software tool called Clarus Analyzer studies the signals collected from the Capture Stations, and can generate .vcd files using a free waveform viewer, or any common external tool from third parties.  Finally, the Clarus Investigator decompresses multiple waveforms, maps the data back to the original RTL design, and reveals equivalent ports and signals in the AutoView Waveform Extrapolation window.  Developers can choose verification levels by electing to use 1, 2, or 3 percent of a design for capture stations, gaining more signal visibility with larger real-estate commitment.

While the Veridae team has decades of experience in EDA tools, the management also is familiar with real-world tradeoffs made in silicon.  Quinton, and Veridae vice president of marketing and sales Greg Wynans, both spent several years at PMC-Sierra, while the company’s CEO, Jim Derbyshire, served the same role at SiGe Semiconductor.  Wynans said that “it’s common for a software developer to say that dedicated hardware for verification is no big deal, but we have worked at making hardware support for verification something that is painless for the developer.”