Webcasts

Reducing Total System Cost with Low-Power 28-nm FPGAs

Do more with less—reduce costs and power, increase productivity, and make the product run faster. Altera’s Cyclone® V FPGAs address these challenges with low system cost, the lowest power of any 28-nm FPGA, and high functionality. Learn more.

Mitigating Soft Errors in DRAM Through Error Correction Code (ECC) on SoC FPGAs

Watch this webcast to learn why mitigating soft errors through ECC improves embedded designs. Understand potential sources and implications of soft errors and learn how Altera’s SoC FPGAs improve error resilience.

Error Correction Code in SoC FPGA-Based Memory Systems

Explore potential sources and implications of soft errors and a method implemented by Altera and Micron Technology to make embedded systems more resilient to soft errors through error detection and correction.

Reducing Power Consumption and Increasing Bandwidth on 28-nm FPGAs

Lower power consumption and higher bandwidth are the dominant design requirements for next-generation high-end applications. Altera’s 28-nm Stratix V FPGAs address these challenges through technological innovation, integration, and reduced power.

Reducing Steps to Achieve Safety Certification

Safety is a critical requirement for machinery that must comply with standards such as the IEC 61508 functional safety standard. Learn successful steps to shorten development and safety certification time with an FPGA implementation of your application.

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Meeting the Low Power Imperative at 28 nm

Whether you want to reduce your carbon footprint, reduce operating costs, or just be more energy efficient, Altera’s 28-nm devices enable system designers to increase their control over power consumption in today’s increasingly power-sensitive applications.

PRODUCT BRIEF: MachXO2 Consumer Applications

The MachXO2™ family of non-volatile infinitely reconfigurable Programmable Logic Devices (PLDs) is designed for low-power consumer applications such as smart phones, GPS devices and PDAs. Combining an optimized look-up table (LUT) architecture with 65-nm embedded Flash process technology, MachXO2 devices provide a flexible “do-it-all” solution for consumer designs.

DATA SHEET: MachXO2 Family

The MachXO2 family of ultra low power, instant-on, non-volatile PLDs has six devices with densities ranging from 256 to 6864 Look-Up Tables (LUTs). In addition to LUT-based, low-cost programmable logic these devices feature Embedded Block RAM (EBR), Distributed RAM, User Flash Memory (UFM), Phase Locked Loops (PLLs), preengineered source synchronous I/O support, advanced configuration support including dual-boot capability and hardened versions of commonly used functions such as SPI controller, I2C controller and timer/counter. These features allow these devices to be used in low cost, high volume consumer and system applications.

Tips and Techniques for 28-nm Design Optimization

Timing closure is of critical importance in high-speed FPGA designs. This white paper focuses on the challenges that affect timing closure and discusses how simple HDL changes can help resolve timing issues and reduce the time needed to achieve timing closure.

Using External Memory Interfaces to Achieve Efficient High-Speed Memory Solutions

Because a fast and robust memory interface is crucial for many designers, Altera provides the fastest, most efficient, and lowest latency memory controllers, which allow designers to work with today’s higher speed memories quickly and easily. Designing with Arria V^® FPGAs not only helps to make designs successful but also ensures that implementation is fast and easy.

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Reduce Power by Removing External Compensation Components with Stratix V FPGAs

Watch this short demonstration of how our 28-nm Stratix V FPGA can provide you with the lowest jitter and bit error rate. In addition, you will see how system cost and power are reduced by removing external compensation components.

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